The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, the smaller feature size may reach the resolution limits of 193-nm lithography. As the demand for even smaller electronic devices has grown recently, there is a need to achieve a high resolution in order to resolve fine, high density, high-resolution patterns.
In order to push the lithographic limit further and to create even smaller semiconductor devices, multiple patterning technology (MPT) techniques are being developed. In a multiple patterning process, a layout of a semiconductor device is decomposed into multiple sub-patterns. Each sub-pattern is defined on a photoresist layer. The sub-pattern in the patterned photoresist layer is transferred to the underlying features of the semiconductor device.